New Techniques for On-Wafer Calibration Over Temperature L. Pattison, N. Buchanan,D. Linton The Department of Electrical and Electronic Engineering The Queen's University of Belfast, Ashby Building, Stranrnillis Road, Belfast, BT9 5AH, N. Ireland, Tel: +44 +(0)1232 274089, Fax +44 +(0)1232 667023 e-mail: lyndon.pattison-ee.qub.ac.uk Abstract - A more convenient approach for on-wafer calibration o

Novel Techniques Simplify Calibration of New Multiport Device Test System David J. Ballo, Hewlett-Packard Company, 1400 Fountaingrove Parkway, Santa Rosa, California, U.S.A. E-mail: david_ballo-hp.com Abstract - This paper focuses on the calibration techniques used in a new test. system from HewlettPackard for measuring 50-ohm multiport devices. The HP 87050E multiport test sets are designed to wo

A New Method to Test and Design Multistage Power Amplifiers Using Load Pull Data Christos Tsironis, Bing Li, Dominique Dubouil, Arnaud Henin Focus Microwaves Inc., Ville 8t Laurent, Quebec, Canada e-mail: info-focus-microwaves.com http://www.focus-microwaves.com Abstract - As an alternative to designing single or twostage power amplifiers using transistor models, nonlinear load pull data can be u

MOS TRANSISTORS ON SOl SUBSTRATE: On- Wafer Measurement for Small-Signal Parameters Extraction Procedure. A.Bracale #*, N.Fel *, V.Ferlet-Cavrois *, D.Pasquet#, J.L.Gautier #, J.L. Pelloie **. # ENSEA, equipe microonde, 6 avenue du Ponceau, 95014 Cergy-Pontoise, France. * CEA, Centre de Bruyeres-Le-Chatel, BP 12,91680 Bruyeres-Le-Chatel, France. Tel: 33 I 69265088. Fax: 33 1692671 16. E-mail serve

APPLICATION OF THE FINITE ELEMENT METHOD TO FET MODEL PARASITIC LUMPED ELEMENTS EXTRACTION E.Larique*, D.Baillargeat*, S.Verdeyme*, M.Aubourg*, J.P.Teyssier*, P.Guillon* C.Zanchi**, J.Sombrin** *IRCOM Faculte des Sciences de Limoges 87060 Limoges Cedex FRANCE **CNES 18 Avenue Edouard Belin 31055 Toulouse Cedex FRANCE Email: larique-ircom.unilim.fr ABSTRACT - A classical method to compute Field Ef

NON LINEAR TRANSMISSION HETEROSTRUCTURE LINE QillNTUPLER LOADED BARRIER VARACTORS BY E. Lheurette, M. Fernandez, X. Melique, P. Mounaix, O. Vanbesien and D. Lippens Institut d'Electronique et de Microelectronique du Nord, D.M.R. C.N.R.S. 8520 Universite des Sciences et Technologies de Lille Avenue Poincare, B.P. 69, 59652 Villeneuve d'Ascq, France Eric.Lheurette-IEMN.univ-Lille1.fr Abstract -T

Analytical, Scaleable Large Signal Noise Model for GaAs and InP MMIC Applications R. Reuter and A. Leven Fraunhofer Institute of Applied Solid-State Physics .TullastraBe 72, D-79108 Freiburg, Gennany Phone: +49 (0) 761-5159820, Fax: +49 (0) 761-5159565 Email: reuter-iaf.fhg.de Abstract - In this paper an analytical large signal noise model for GaAs- and InP-based HFETs is presented. The capability

A STUDY OF LAYOUT STRATEGIES FOR LOWERING RF CMOS DEVICE TOLERANCES Troels Emil Kolding, Member, IEEE Aalborg University, RF Integrated Systems & Circuits (RISC) group, Denmark. eMail: tek-kom.auc.dk WWW: http://www.tele.auc.dk/risc/index.html Abstract - Although tolerance levels for CMOS devices at gigahertz frequencies constitute a major challenge to RF-IC designers, little has been published ab

An Empirical PHEMT Model and Its Verification in PCS CDMA System Jiang Cao, Xinwei Wang *, Fujiang Lin, Hiroshi Nakamura*, Rajinder Singh Institute of Microelectronics, Singapore 11 Science Park Road, Singapore 117685,Singapore caojiang-ime.org.sg,Tel:65-7705526,Fax:65-7745754 *Oki TechnoCentre (Singapore)Pte Ltd 20 Science Park Road #02-06/10,Singapore 117674,Singapore Abstract A new empirical

2 X 2 Spatial Power Combining Array of Planar Radiating Oscillator using Butterfly-Shaped Patch Element Masami MURATA *,** and Toshiaki MATSUI ** *University of Electro-Communications(UEC), 1-5-1, Choufugaoka, Choufu-shi, Tokyo 182-8585, Japan. **Communications Research Laboratory(CRL), Ministry of Posts and Telecommunications, 4-2-1, Nukui-Kitamachi, Koganei-shi, Tokyo 184-8795, Japan. Phone: +81