A 38-GHz demodulator with high image rejection in 65 nm-CMOS process
Tian-Wei Huang, Yi-Cheng Huang, Chen Chien, Kun-Chan Chiang, Jeng-Han Tsai
A high image rejection 38 GHz demodulator in TSMC 65-nm CMOS process is presented. To achieve better than ?40 dBc image rejection ratio (IRR), a low I/Q mismatch 45° LO power splitter of sub-harmonic mixer is proposed. In this design, the 45° LO power splitter is composed of a Wilkinson divider, a series delay line with electrical length of 45° on one side of the divider, and a shunt 90° transmiss